1. Field of the Invention
The present invention relates to an information processing system having a plurality of processors and a controller such as a processor having a plurality of interrupt terminals but without a multiple interrupt function, and a controller and a processor used in such an information processing system.
2. Description of the Related Art
FIG. 1 is a block diagram of a control processor of a conventional multiprocessor system which is an example of a system of this type. Referring to FIG. 1, a control processor 20a includes first, second, and third interrupt request signal input terminals 40, 46, and 50 for receiving an interrupt request signal from another processor in the system, first, second, and third interrupt request acceptance signal output terminals 42, 48, and 52 to provide an interrupt request acceptance signal for each processor. Control processor 20a further includes an interrupt processing circuit 22a connected to terminals 40, 42, 46, 48, 50, and 52 for carrying out a predetermined interrupt process in response to the first among input interrupt request signals, a bus 28 connected to interrupt processing circuit 22a and other units (not shown) of processor 20a, and an interface 26 between bus 28 and a system bus 38 of the multiprocessor system.
Interrupt processing circuit 22a includes first, second, and third interrupt request generation signal output circuits 32, 34a, and 36a connected to first, second, and third interrupt signal input terminals 40, 46, and 50, respectively, and a sequence control circuit 30 connected to interrupt request generation signal output circuits 32, 34a, 36a, to first, second and third interrupt request acceptance signal output terminal 42, 48, 52, and to bus 28 for carrying out a predetermined sequence control at the time of interrupt.
Sequence control circuit 30 does not have a multi interrupt function and processes all the input interrupt request generation signals with equal priority. More specifically, sequence control circuit 30 carries out an interrupt process with respect to the first interrupt request generation signal, and does not accept another interrupt request until that interrupt process is completed. If interrupt requests are generated at the same time, only the interrupt request determined according to a predetermined priority level is accepted. Sequence control circuit 30 provides an interrupt request input acceptance signal 70 when any interrupt request generation signal is accepted. Interrupt request input acceptance signal 70 is inverted by an invert circuit (inverter 71) to be applied to first, second and third interrupt request generation signal output circuits 32, 34a, and 36a. When a predetermined interrupt process is completed, sequence control circuit 30 provides an interrupt process end signal 72. Interrupt process end signal 72 is applied to first, second and third interrupt request generation signal output circuits 32, 34a, and 36a.
Each of interrupt request generation signal output circuits 32, 34a, 36a has a similar structure. For example, first interrupt request generation signal output circuit 32 includes a flipflop 54 with an 1 bit set/reset function, and an OR circuit 56. It is assumed that each signal in the signal multiprocessor system complies with a negative logic unless otherwise stated. The set terminal of flipflop 54 is applied with an interrupt request input acceptance signal 70 inverted by invert circuit 71. OR circuit 56 has one input connected to the output of flipflop 54. OR circuit 56 has the other input connected to first interrupt request signal input terminal 40. The output of OR circuit 56 is connected to first interrupt request generation signal input terminal 41 of sequence control circuit 30.
Similarly, second interrupt request generation signal output circuit 34 includes a flipflop 60 and an OR circuit 62. OR circuit 62 has one input connected to second interrupt request signal input terminal 46. The output of OR circuit 62 is connected to second interrupt request generation signal input terminal 47 of sequence control circuit 30.
Third interrupt request generation signal output circuit 36a includes a flipflop 66 and an OR circuit 68. OR circuit 68 has one input connected to third interrupt request signal input terminal 50. The output of OR circuit 68 is connected to third interrupt request generation signal input terminal 51 of sequence control circuit 30.
The conventional control processor 20a shown in FIG. 1 operates as follows. It is assumed that sequence control circuit 30 is not during an interrupt process execution. Each of flipflops 54, 60 and 66 is reset, and each output attains a low level (refer to as "L" level hereinafter). If there is no input of an interrupt request signal from the processors, they attain a high level (referred to as "H" level herein after), and the outputs of OR circuits 56, 62 and 68 attain an H level.
Suppose that an interrupt request signal is entered to first interrupt request signal input terminal 40. More specifically, the signal level of first interrupt request signal input terminal 40 changes to the L level from the H level. The output of OR circuit 56 also attains the L level, whereby an interrupt request generation signal is applied to first interrupt request generation signal input terminal 41.
Sequence control circuit 30 provides an interrupt request input acceptance signal 70 to the respective set terminals of flipflops 54, 60 and 66 when an interrupt request generation signal is accepted. This interrupt request input acceptance signal 70 changing from the H level to the L level is inverted by invert circuit 71. Flipflops 54, 60 and 66 are set at the rising edge thereof. The outputs of flipflops 54, 60 and 66 attain the H level. As a result, the outputs of OR circuits 56, 62 and 68 all attain the H level regardless of the value of the input interrupt request signal. In other words, an interrupt request signal will be no longer accepted.
When an interrupt request signal is accepted, sequence control circuit 30 initiates the execution of a predetermined interrupt process. Sequence control circuit 30 provides an interrupt process end signal 72 when the execution of this interrupt process is completed. Interrupt process end signal 72 is a pulse of negative logic having a predetermined pulse width. Flipflops 54, 60 and 66 are reset at the rising edge of interrupt process end signal 72. The signal applied to one input of each of OR circuits 56, 62 and 68 from flipflops 54, 60, and 66, respectively, attains the L level. If an interrupt request signal is entered to each of interrupt request signal input terminals 40, 46 and 50, that signal will be provided to sequence control circuit 30.
When sequence control circuit 30 accepts an interrupt request signal from first interrupt request signal input terminal 40 as described above, an interrupt request acceptance signal is simultaneously provided to the relevant processor via terminal 42. The processor generating the interrupt request signal initiates a predetermined process in response to this interrupt request acceptance signal.
When flipflops 54, 60 and 66 are set by an interrupt request input acceptance signal 70, the output of each of OR circuits 56, 62 and 68 attains the H level regardless of the presence of an interrupt request signal. Therefore, a signal indicating generation of an interrupt request is not applied to sequence control circuit 30 even if an interrupt request signal is input. The initiated interrupt process can be executed until the end thereof. When the interrupt processing is completed, flipflops 54, 60 and 66 are reset by an interrupt process end signal 72. As a result, acceptance of another interrupt request signal is allowed.
FIG. 2 is a block diagram of a DCT processor 92a for carrying out a predetermined process, for example a DCT (Discrete Cosine Transform) process used in a multiprocessor system including the control processor shown in FIG. 1. Referring to FIG. 2, DCT processor 92a includes an interrupt request signal output terminal 98 connected to first interrupt request signal input terminal 40 and first interrupt request acceptance signal output terminal 42 (refer to FIG. 1), and an interrupt request acceptance signal input terminal 100. Terminals 98 and 100 are both connected to a processor 120. DCT processor 92a further includes a local memory 126, and a bus 122 connecting local memory 126 and processor 120. Bus 122 is connected to system bus 38 by an interface 124.
DCT processor 92a operates as follows. DCT processor 92a functions to process image data including a great amount of data for every 1 block (for example, 1 block is 8 lines.times.8 pixels). The image data is already stored in a main memory not shown in the system. Prior to the process of 1 block of image data, DCT processor 92a must read out 1 block of image data from the system main memory to write the same into local memory 126. Similarly, data after the process must be read out from local memory 126 to be written into the main memory of the system.
In such cases, contention of access from each processor occurs with respect to the system memory shared in the system. To solve such contention, a processor including DCT processor 92 carries out an operation set forth in the following.
When image data is to be read out from the system memory, processor 120 provides an interrupt request signal from terminal 98. This interrupt request signal is applied, for example, to first interrupt request signal input terminal 40 of control processor 20a shown in FIG. as described above.
If sequence control circuit 30 of FIG. 1 attains a state that allows interrupt, this interrupt request signal is accepted, and an interrupt request acceptance signal is returned to interrupt request acceptance signal input terminal 100. In response, processor 120 initiates a process of data transfer from the main memory.
Data read out from the main memory and data writing into local memory 126 are carried out as follows. Referring to FIG. 1, if an interrupt request from DCT processor 92a is accepted, sequence control circuit 30 invokes an interrupt process to read out data of a predetermined block from the main memory not shown. The read out data is applied to interface 124 of FIG. 2 via system bus 38. Processor 120 writes the data provided via interface 124 into local memory 126. When this reading and writing of 1 block of data is completed, the interrupt process of sequence control circuit 30 ends. An interrupt request signal applied to control processor 20a is not accepted during execution of the interrupt process. The other processors attain a standby state until their interrupt requests are accepted.
When 1 block of image data is written into local memory 126, DCT processor 92a carries out a predetermined DCT process on each data. When the predetermined process on all the 1 block of data is completed, processor 120 provides an interrupt request signal to processor 20a via interrupt request signal output terminal 98. If this interrupt request signal is accepted, data is read out from local memory 126 to be provided to interface 124. Control processor 20a initiates an interrupt process, whereby data is read out to system bus 38 via interface 124 to be written into the system memory. Reading out data from local memory 126 and writing the data into the main memory are carried out as interrupt processes. If a process to a subsequent block is to be carried out in succession, data of the next block is read out from the main memory to be written into local memory 126 succeeding the interrupt process. During this interrupt process, input of an interrupt request signal to control processor 20a is not accepted.
When there is a possibility of access contention or the like with respect to the resource shared by the system, such contention was solved by control processor 20a.
FIG. 3 schematically shows an operation of a conventional multiprocessor system. In this system, first to third processes are to be carried out by three processors.
Referring to FIG. 3, it is assumed that a first interrupt request is generated at time t1, and the first interrupt request is accepted at time t2. Execution of the first interrupt process is initiated at time t2. This first interrupt process ends at time t3. At time t4, a second interrupt request signal is entered. At time t5, this second interrupt request signal is accepted, whereby the second interrupt process is initiated.
It is assumed that a third interrupt request is generated at time t6, and the first interrupt request is generated again at time t7 during the initiation and completion of the second interrupt process (time t5-time t8). Because flipflops 54 and 66 are set when the second interrupt request is accepted as described above, the third interrupt request and the first interrupt request are not accepted at system control circuit 30 and forced to wait until the second interrupt process is completed.
When the second interrupt process ends, the third interrupt request is accepted at time t9, whereby execution of the third interrupt process is initiated. The first interrupt request process is not accepted, resulting in a standby state during execution of the third interrupt process. When the third interrupt process ends at time t10, the first interrupt is accepted at time t11. Then, execution of the first interrupt process is initiated, and ends at time t12.
Each processor generates an interrupt request to the control processor when access to a common resource is requested. Each processor causes a predetermined interrupt process to be initiated by the control processor while carrying out access to the common resource. When the common resource is accessed and data required for processing is applied to each processor, each processor carries out processing independent of the control processor and other processors. When the process is completed and access to the common resource is required again, an interrupt request signal is provided to carry out access to the common resource under the control of the control processor.
When an interrupt request signal is input from different interrupt request input terminals simultaneously, the interrupt process is accepted according to predetermined priority levels.
Thus, in an information processing system having a plurality of processors, an interrupt request from a processor is not accepted once an interrupt process of another processor is initiated. There is difference in the amounts of load of the processes carried out by the processors. The processing execution of a processor of heavy load is time consuming to increase the processing time period of the entire system. Therefore, acceptance of such an interrupt process should be carried out prior to other processors. However, the above-described information processing system lacking a multiple interrupt function simply carries out acceptance according to the order of interrupt request generation even if it is apparent that a certain processor should be served first. Because the process to be carried out by a processor of the greatest load is not carried out satisfactorily, the process in other processors using the data result thereof is often made to standby. Therefore, the operation of the entire system was not efficient. This problem can generally be solved by using a controller having a multiple interrupt function. However, the hardware of such a controller is complicated and expensive. There was also a problem that the process required in the controller will become complicated.